Towards a Method for VLSI Circuit Reverse Engineering

This paper tackles the VLSI circuit reverse engineering problem. Actual VLSI circuits are made of several millions of transistors or hundreds of thousands of logical gates. Whether it be for circuit verification, functional abstraction, or simply circuit understanding, reverse engineering aims at building a hierarchy from the transistor level, to gate level, to register level, up to more complex components. The idea is to transform the circuit into a target graph and to look for instances of sub-circuits as subgraph patterns in the original graph. In this work, we propose to cast the subgraph isomorphism as a constraint satisfaction problem, where an isomorphism is expressed by a set of constraints and filters.